1. Field of the Invention
The present invention relates to a circuit in a semiconductor memory device or chip, where an internal power supply voltage and an external power supply voltage are used and, in particular, to a power supply voltage detecting circuit for sensing a specific voltage level so that the reliability of a chip can be ensured for a long time at a high power supply voltage. The present application is based on Korean Application No. 20768/1995 which is incorporated herein by reference for all purposes.
2. Description of the Related Art
Generally, a semiconductor memory device operates by way of an internal power supply voltage (hereinafter, referred to as IV.sub.cc) an external power supply voltage (hereinafter, referred to as EV.sub.cc) and a control signal, and satisfies AC and DC characteristics of a product at a given power supply voltage interval thereof. Also, a power supply voltage detecting circuit capable of sensing a specific voltage level is necessarily required for enabling a circuit which operates over a specific voltage (V.sub.cc ext=6.about.8V) such as a burn-in test. However, the power supply voltage detecting circuit as described above does not ensure the reliability of the chip for a long time at a high power supply voltage.
Further, the voltage applied from the external power supply can be used to energize the semiconductor memory device or chip and the reliability of the chip can be maximized by using an internal voltage converter (hereinafter, referred to as IVC) which limits the internal power supply voltage IV.sub.cc having a given voltage level.
FIG is a circuit diagram illustrating a prior art power supply voltage detecting circuit for use in a semiconductor memory device and FIG. 2 is a wave form of the prior art power supply voltage detecting circuit as shown in FIG. 1.
With reference to FIGS. 1 and 2, the construction and the operation of the prior art power supply voltage detecting circuit will be explained in detail hereinafter.
The prior art power supply voltage detecting circuit, as illustrated in FIG. 1, comprises a reference voltage generator 10 having a given voltage characteristic depending on the external power supply voltage EV.sub.cc. The reference voltage generator 10 outputs a reference voltage V.sub.ref. A differential amplifier 100 compares and amplifies the reference voltage V.sub.ref and an output voltage V.sub.a, wherein the output voltage V.sub.a and its output level are simultaneously varied with the external power supply voltage EV.sub.cc as shown by the graph in FIG. 2.
An explanation on the operation of the prior art power supply voltage detecting circuit will be briefly given below,
The external power supply voltage EV.sub.cc is supplied to the reference voltage, generator 10, first and second P-type transistors 1 and 2, and first and second resistors 8 and 9. An output voltage V.sub.out of the differential amplifier 100 is then supplied to first and second inverters 6 and 7.
Furthermore, in accordance with the variation of the external power supply voltage EV.sub.cc, the output voltage V.sub.a which simultaneously varies proportionally with its output level, can be seen in following expression: EQU V.sub.a =EV.sub.cc .times.R.sub.8 /(R.sub.8 +R.sub.9)
where R.sub.6 is the resistance value of first resistor 8 and R.sub.9 is the resistance value of second resistor 9 as shown in the circuit of FIG. 1.
As can be seen in the above expression, inasmuch as the output voltage V.sub.a in an external power supply voltage region I as set forth in FIG. 2 is lower than the outpost voltage V.sub.ref therein, when the output voltages V.sub.a and V.sub.ref are applied as inputs of the differential amplifier 100, the output voltage V.sub.out goes to a logic "low" state. Thus, when V.sub.a &lt;V.sub.ref, then V.sub.out ="low" state.
Moreover, because the output voltage V.sub.a in an external power supply voltage region II, as set forth in FIG. 2, is higher than the output voltage V.sub.ref therein, the output voltage V.sub.out of the differential amplifier 100 goes to a logic "high" state of 5.about.7V. In this case, in the logic "high" state of the external power supply voltage EV.sub.cc, a greater stress is applied to a gate of the first inverter 6 for as long as V.sub.a &gt;V.sub.ref. As a result, the reliability of the chip may be reduced.
In addition, since this results in bias transistor 5 being switched on when the chip is not being used and consequently placed in a stand-by state, it results in a problem in that the current can flow at all times through transistor 5.